Toshiba TLCS-900/L1 Series Manual page 4

Original cmos 16-bit microcontroller
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(4) External memory expansion
Expandable up to 106 Mbytes (shared program/data area)
Can simultaneously support 8-/16-bit width external data bus
Dynamic data bus sizing
Separate bus system
(5) 8-bit timers: 4 channels
(6) General-purpose serial interface: 2 channels
UART/Synchronous mode: 2 channels
IrDA Ver.1.0 (115.2 kbps) mode selectable: 1 channel
(7) Serial bus interface: 1 channel
I
C bus mode/clock synchronous mode selectable
2
(8) Timer for real-time clock (RTC)
Based on TC8521A
(9) 10-bit AD converter: 8 channels
(10) Watchdog timer
(11) Melody/alarm generator
Melody: Output of clock 4 to 5461 Hz
Alarm: Output of the 8 kinds of alarm pattern
Output of the 5 kinds of interval interrupt
(12) Chip select/wait controller: 4 channels
(13) Memory management unit
Expandable up to 106 Mbytes (4 local areas/8-bank method)
(14) Interrupts: 37 interrupts
9 CPU interrupts:
23 internal interrupts: 7 priority levels are selectable
5 external interrupts: 7 priority levels are selectable
(15) Input/output ports: 35 pins (at external 16-bit data bus memory)
(16) Standby function
Three HALT modes: IDLE2 (Programmable), IDLE1 and STOP
(17) Triple-clock controller
Clock doubler (DFM) circuit is inside
Clock gear function: Select a high-frequency clock fc/1 to fc/16
Slow mode (fs = 32.768 kHz)
(18) Operating voltage
V
= 2.7 V to 3.6 V (fc max = 33 MHz)
CC
V
= 1.8 V to 3.6 V (fc max = 10 MHz)
CC
(19) Package
100-pin QFP: LQFP100-P-1414-0.50F
Chip form supply also available. For details, contact your local Toshiba sales
representative.
Software interrupt instruction and illegal instruction
(among 4 interrupts are selectable edge mode)
91C824-2
TMP91C824
2008-02-20

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