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(P83)
ADTRG
AN0 to AN7 (P80 to P87)
10-bit 8-channel
AVCC, AVSS
VREFH, VREFL
TXD0 (PC0)
SIO/UART/IrDA
RXD0 (PC1)
SCLK0/
(PC2)
CTS
0
TXD1 (PC3)
RXD1 (PC4)
SCLK1/
(PC5)
CTS
1
OPTRX0, SCK (P70)
OPTTX0, SO/SDA(P71)
SI/SCL (P72)
TA0IN (PB0)
TA1OUT (PB1)
TA3OUT (PB2)
XWA
XBC
AD
XDE
converter
XHL
XIX
XIY
XIZ
XSP
32 bits
(SIO0)
SR
SIO/UART
(SIO1)
Serial bus
I/F(SBI)
8-bit timer
(TMRA0)
8-bit timer
(TMRA1)
8-bit timer
(TMRA2)
8-bit timer
WDT
(TMRA3)
(Watchdog timer)
Port 6
8-Kbyte RAM
Port 8
Port B
Port C
Port D
Figure 1.1 TMP91C824 Block Diagram
91C824-3
W A
B C
D E
H-OSC
H L
IX
IY
Clock gear,
IZ
SP
Clock doubler
F
L-OSC
Port 1
Port 2
Port Z
Port 5
CS/WAIT
controller
(4 blocks)
MMU
Interrupt
controller
Melody/
Alarm-out
RTC
TMP91C824
DVCC [2]
DVSS [2]
X1
X2
EMU0
EMU1
XT1
XT2
SCOUT (PD5)
RESET
AM0
AM1
D0 to D7
A0 to A7
A8 to A15
P10 to P17 (D8 to D15)
P20 to P27 (A16 to A23)
RD
WR
(PZ2)
HWR
R/
(PZ3)
W
(P54)
BUSRQ
(P55)
BUSAK
(P56)
WAIT
to
(P60 to P63),
CS0
CS3
to
CS2A
CS
2
E
(P62, P64 to P67)
(P60 to P67)
NMI
INT0 to INT3 (PB3 to PB6)
MLDALM (PD7)
,
(PD6)
ALARM
MLDALM
( ): Initial function after reset
2008-02-20
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