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(2) Soft start function
In addition to starting the micro DMA function by interrupts, TMP91C824 includes
a micro DMA software start function that starts micro DMA on the generation of the
write cycle to the DMAR register.
Writing "1" to each bit of DMAR register causes micro DMA once (If write "0" to
each bit, micro DMA doesn't operate). At the end of transfer, the corresponding bit of
the DMAR register which support the end channel are automatically cleared to "0".
Only one-channel can be set for DMA request at once. (Do not write "1" to plural
bits.)
When writing again "1" to the DMAR register, check whether the bit is "0" before
writing "1". If read "1", micro DMA transfer isn't started yet.
When a burst is specified by DMAB register, data is continuously transferred until
the value in the micro DMA transfer counter is "0" after start up of the micro DMA. If
execute soft start during micro DMA transfer by interrupt source, micro DMA
transfer counter doesn't change. Don't use Read-modify-write instruction to avoid
writing to other bits by mistake.
Symbol
Name
Address
DMA
89H
DMAR
request
(Prohibit
register
RMW)
(3) Transfer control registers
The transfer source address and the transfer destination address are set in the
following registers in CPU. Data setting for these registers is done by an LDC cr, r
instruction.
Channel 0
DMAS0
DMAD0
Channel 3
DMAS3
DMAD3
32 bits
7
6
5
DMA source address register 0
DMA destination address register 0 : Only use LSB 24 bits
DMAC0
DMA counter register 0
DMAM0
DMA mode register 0
DMA source address register 3
DMA destination address register 3
DMAC3
DMA counter register 3
DMAM3
DMA mode register 3
8 bits
16 bits
91C824-43
4
3
2
DMAR3
DMAR2
R/W
0
0
DMA request
: Only use LSB 24 bits
: 1 to 65536
TMP91C824
1
0
DMAR1
DMAR0
0
0
2008-02-20
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