Toshiba TLCS-900/L1 Series Manual page 23

(2) Clock gear controller
When the high-frequency clock fc is selected by setting SYSCR1<SYSCK> = 0, f
is set according to the contents of the clock gear select register SYSCR1<GEAR0:2> to
either fc, fc/2, fc/4, fc/8 or fc/16. Using the clock gear to select a lower value of f
reduces power consumption.
Example 3:
Changing to a high-frequency gear
SYSCR1 EQU 00E1H
LD (SYSCR1),XXXX0000B
X: Don't care
(High-speed clock gear changing)
To change the clock gear, write the register value to the SYSCR1<GEAR2:0>
register. It is necessary the warm-up time until changing after writing the register
value.
There is the possibility that the instruction next to the clock gear changing
instruction is executed by the clock gear before changing. To execute the instruction
next to the clock gear switching instruction by the clock gear after changing, input
the dummy instruction as follows (Instruction to execute the write cycle).
Example:
SYSCR1 EQU 00E1H
LD (SYSCR1),XXXX0001B
LD (DUMMY), 00H
Instruction to be executed after clock gear has changed
(3) Internal clock terminal out function
It can out internal clock (f
PD5 pin function is set to SCOUT output by the following bit setting.
: PDFC<PD5F> = 1
Output clock select
: Refer to SYSCR2<SCOSEL> bit setting
HALT Mode NORMAL
SCOUT Select SLOW
<SCOSEL> = 0
<SCOSEL> = 1
; Changes f
; Changes f
SYS
; Dummy instruction
or fs) from PD5/SCOUT.
SYS
IDLE2
fs clock out
f clock out
SYS
91C824-21
TMP91C824
to fc/2.
SYS
to fc/4.
HALT Mode
IDLE1 STOP
0 or 1 fix out
2008-02-20
FPH
FPH