Toshiba TLCS-900/L1 Series Manual page 149

* Clock state
Main settings
7 6 5 4 3 2 1 0
← X X − − − − 0 −
PCCR
SC0MOD0 ← − − 1 − 1 0 0 1
← − 0 1 − − − − −
SC0CR
← 0 0 0 1 0 1 0 1
BR0CR
← − − − − − 1 0 0
INTES0
Interrupt processing
← SC0CR AND 00011100
Acc
≠ 0 then ERROR
if Acc
← SC0BUF
Acc
X: Don't care, − : No change
(4) Mode 3 (9-bit UART mode)
9-bit UART mode is selected by setting SC0MOD0<SM1:0> to 11. In this mode
parity bit cannot be added.
In the case of transmission the MSB (9th bit) is written to SC0MOD0<TB8>. In the
case of receiving it is stored in SC0CR<RB8>. When the buffer is written and read,
the MSB is read or written first, before the rest of the SC0BUF data.
Wakeup function
In 9-bit UART mode, the wakeup function for slave controllers is enabled by setting
SC0MOD0<WU> to 1. The interrupt INTRX0 occurs only when<RB8> = 1.
TXD RXD TXD
Master
Note: The TXD pin of each slave controller must be in Open-drain output mode.
Figure 3.9.23 Serial Link Using Wakeup Function
System clock:
Clock gear:
Prescaler clock: System clock
Set PC1 to function as the RXD0 pin.
Enable receiving in 8-bit UART mode.
Add even parity.
Set the transfer rate to 9600 bps.
Enable the INTTX0 interrupt and set it to interrupt level 4.
Check for errors.
Read the received data.
RXD TXD
Slave 1 Slave 2
91C824-147
TMP91C824
High frequency (fc)
1 (fc)
RXD TXD
Slave 3
2008-02-20
RXD