Toshiba TLCS-900/L1 Series Manual page 56

Table 3.5.3 I/O Registers and Specifications (2/2)
Port Pin Name
Port 8 P80 to P87 Input port
AN0 to 7 input
P83
Port B PB0 to PB6 Input port
Output port
PB0 TA0IN input
PB1 TA1OUT output
PB2 TA3OUT output
PB3 INT0 input
PB4 INT1 input
PB5 INT2 input
PB6 INT3 input
Port C PC0 to PC5 Input port
Output port
PC0 TXD0 output
PC1 RXD0 input
PC2 SCLK0 input
SCLK0 output
PC3 TXD1 output
PC4 RXD1 input
PC5 SCLK1 input
SCLK1 output
Port D PD5 to PD7 Output port
PD5 SCOUT output
PD6
PD7 MLDALM output
Port Z PZ2 to PZ3 Input port (without PU)
Input port (with PU)
Output port
PZ2
PZ3
X: Don't care
Note 1: Port 1 is only use for Port or DATA bus (D8 to D15) by setting AM1 and AM0 pins.
Note 2: As for input ports of SIO0 and SIO1 (OPTRX0, OPTTX0, TXD0, RXD0, SCLK0,
RXD1, SCLK1,
CTS1
output latch register Pn of each port.
Note 3: In case using P71 and P72 for SDA and SCL as open-drain ports, set to P7ODE
<ODEP71:72>.
Note 4: In case using P80 to P87 for analog input ports of AD converter, set to ADMOD1 <ADCH2:0>.
Note 5: In case using P83 for
Note 6: In case using PC1 for RXD0 port, set 0 to P7FC2<P70F2>.
Specification
(Note 4)
input (Note 5)
ADTRG
(Note 2)
(Note 2) (Note 6)
(Note 2)
(Note 2)
input (Note 2)
CTS 0
(Note 2)
(Note 2)
(Note 2)
(Note 2)
input (Note 2)
CTS 1
output
ALARM
output
MLDALM
output
HWR
output
R / W
), logical selection for output data or input data is determined by the
input port, set to ADMOD1<ADTRGE>.
ADTRG
91C824-54
TMP91C824
I/O Register
Pn PnCR PnFC PnFC2
X
None
X
X
X 0 0
X 1 0
X 0 None
X 1 1
X 1 1
X 0 1
X 0 1
X 0 1
X 0 1
X 0 0
X 1 0
1 1 1
1 0 None
1 0 0
None
1 1 1
1 0 0
1 1 1
1 0 None
1 0 0
1 1 1
1 0 0
X 0
X 1
None
1 1
0 1
X 1
0 0 0
1 0 0
X 1 0
X 1 1
X 1 1
CTS0
2008-02-20
, TXD1,