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(2) Vcc = 2.0 V ± 10%
No.
Parameter
1 f
period (= x)
FPH
2 A0 to A15 valid →
RD
rise → A0 to A23 hold
3
RD
rise → A0 to A23 hold
4
WR
5 A0 to A23 valid →
RD
fall → D0 to D15 input
6
RD
low width
7
RD
rise → D0 to D15 hold
8
RD
9
low width
WR
10 D0 to D15 valid →
WR
rise →D0 to D15 Hold
11
WR
12 A0 to A23 valid →
WAIT
fall →
13
/
RD
WR
WAIT
14 A0 to A23 valid → Port input
15 A0 to A23 valid → Port hold
16 A0 to A23 valid → Port valid
AC measuring conditions
•
Output level: High = 0.7 V, Low = 0.3 V, CL = 50 pF
•
Input level:
Note: Symbol x in the above table means the period of clock f
f
for CPU core. The period of f
SYS
high/low oscillator frequency.
Symbol
tFPH
/
fall
WR
tAC
tCAR
tCAW
/
fall
tAD
WR
tRD
tRR
tHR
tWW
rise
tDW
tWD
(1 + N) WAIT
input
tAW
mode
(1 + N) WAIT
hold
tCW
mode
tAPH
tAPH2
tAPO
High = 0.9 V, Low = 0.1V
depends on the clock gear setting or the selection of
FPH
91C824-223
Variable
10 MHz
Min
Max
Min
100
31250
100
x − 46
54
0.5x − 30
20
x − 26
74
3.5x − 48
2.5x − 48
2.5x − 30
220
0
0
2.0x − 30
170
1.5x − 70
80
x − 50
50
3.5x − 120
2.5x + 0
250
3.5x − 50
3.5x
350
3.5x + 60
, it's half period of the system clock
FPH
TMP91C824
Unit
Max
ns
ns
ns
ns
302
ns
202
ns
ns
ns
ns
ns
ns
230
ns
ns
300
ns
ns
410
ns
2008-02-20
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