Toshiba H1 Series Data Book page 106

32bit micro controller tlcs-900/h1 series
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Sample2) Calculation examples for CPU + LDMA
Conditions 1:
CPU operation speed (f
Display RAM
Display size
Display quality
Refresh rate
Calculation example 1:
t
(LDMA)
STOP
LHSYNC [period: s] = 1/70 [Hz] /(COM+20=260) = 54.95 [ μ s]
CPU bus stop rate
Conditions 2:
CPU operation speed (f
Display RAM
Display size
Display quality
Refresh rate
Calculation example 2:
t
(LDMA)
STOP
LHSYNC [period: s]
CPU bus stop rate
)
: 60 MHz
SYS
: Internal RAM
: QVGA (320seg × 240com)
: 65536 colors (TFT)
: 70 Hz (including 20 clocks of dummy cycles)
= ((SegNum × K / 8) × t
) + (1 / f
LRD
= ((320 × 16 / 8) × 1 / f
[Hz] / 4) + (1 / f
SYS
= ((640) × 16.67 [ns] / 4) + 16.67 [ns]
= 2.68 [ μ s]
= t
(LCD)[s] / LHSYNC [period: s]
STOP
= 2.68 [ μ s] / 54.95 [ μ s] = 4.88 [%]
)
: 10 MHz
SYS
: 16-bit external SRAM (0 waits)
: QVGA (240seg × 320com)
: 4096 colors (STN)
: 100 Hz (0 dummy cycles)
= (SegNum × K / 8) × tLRD
= (240 × 12 / 8) × ( 2 + wait count) / f
= (360) × 200 [ns] / 2
= 36 [ μ s]
= 1/100 [Hz] / (COM = 240) = 41.67 [ μ s]
= t
(LCD)[s] / LHSYNC [period: s]
STOP
= 36 [ μ s] / 41.67 [ μ s] = 86.40 [%]
92CZ26A-103
[Hz])
SYS
[Hz])
SYS
[Hz] / 2
SYS
TMP92CZ26A

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