Toshiba H1 Series Data Book page 111

HDMATR
bit Symbol
(097FH)
Read/Write
After reset
Function
Note: Read-modify-write instructions can be used on this register.
By writing "87H" to the HDMATR register, the maximum HDMA time is set to 29.9 [μs]
(256 × 7 × (1 / f
LHSYNC [period:s] = 54.95 [μs], it is assumed that HDMA transfer occurs once during
LHSYNC [period:s].
Since SDRAM is auto-refreshed once or less in 5.47 [μs]:
t
STOP
The time LDMA, ARDMA, and HDMA all occupy the bus is defined as:
t
STOP
Based on the above, the CPU bus stop rate is calculated as follows:
CPU bus stop rate
Note: To be precise, the bus assert time and RAM access time are added each time the HDMA transfer time is
forcefully terminated at 29.9 [ μ s].
7 6
DMATE DMATR6 DMATR5
0 0
Timer
operation The value to be set in <DMATR6:0> should be obtained by
0: Disable
1: Enable
)). Since HDMA start interval [period:s] = 83.33 [ms] is longer than
SYS
= 2 / f
(ARDMA)
SYS
(LDMA･ARDMA･HDMA)
= t
STOP
= (5.47 [μs] + 33.33 [ns]+29.9 [μs]) / 54.95 [μs] = 64.42 [%]
HDMATR Register
5 4 3
DMATR4 DMATR3
R/W
0 0 0
Maximum bus occupancy time setting
"maximum bus occupancy time / (256/fSYS)".
"00H" cannot be set.
[Hz] = 33.33 [ns]
(LDMA･ARDMA･HDMA) [s] / LHSYNC [period:s]
92CZ26A-108
TMP92CZ26A
2 1
DMATR2 DMATR1 DMATR0
0 0
0
0