Toshiba H1 Series Data Book page 96

(4) HDMACBn (DMA Transfer Count B Setting Register)
The HDMACBn register is used to set the number of times a DMA request is to be made.
HDMACBn contains 16 bits and can specify up to 65536 requests (0001H = one request,
FFFFH = 65535 requests, 0000H = 65536 requests). When the transfer count B is updated
by DMA execution, HDMACBn is also updated.
HDMACB0 to HDMACB5 have the same configuration.
HDMACBn
bit Symbol DnCB7
Read/Write
After reset
Function
bit Symbol DnCB15
Read/Write
After reset
Function
Channel 0
Channel 1
Channel 2
Channel 3
Channel 4
Channel 5
Note: Read-modify-write instructions can be used on all these registers.
HDMACBn Register
7 6 5
DnCB6 DnCB5
0 0 0
15 14 13
DnCB14 DnCB13
0 0 0
Transfer count B Transfer count B
[15: 8] [7: 0]
HDMACB0
(090BH) (090AH)
HDMACB1
(091BH) (091AH)
HDMACB2
(092BH) (092AH)
HDMACB3
(093BH) (093AH)
HDMACB4
(094BH) (094AH)
HDMACB5
(095BH) (095AH)
Figure 3.6.5 HDMACBn Register
92CZ26A-93
4 3
DnCB4 DnCB3
R/W
0 0
Transfer count B [7:0] for DMAn
12 11
DnCB12 DnCB11
R/W
0 0
Transfer count B [15:8] for DMAn
TMP92CZ26A
2 1 0
DnCB2 DnCB1 DnCB0
0 0 0
10 9 8
DnCB10 DnCB9 DnCB8
0 0 0