Toshiba H1 Series Data Book page 198

(7) Basic bus timing
(a) External read/write cycle (0 waits)
SDCLK
(60 MHz)
CSn
A23 to A0
,
RD SRxxB
D15 to D0
SRWR
WRxx
D15 to D0
(b) External read/write cycle (1 wait)
SDCLK
(60 MHz)
CSn
A23 to A0
,
RD SRxxB
D15 to D0
SRWR
WRxx
D15 to D0
T1
,
SRxxB
Output
T1
,
SRxxB
92CZ26A-195
T2
Read
Input
Write
TW T2
Input
Output
TMP92CZ26A
Read
Write