(2) SDRAM write timing (Single write mode, <SPRE>=1)
SDCLK
t
t
CH
CL
SDxxDQM
SDCS
SDRAS
SDCAS
SDWE
A0~A9
A10
A11~A15
D0~D15
t
CK
t
RCD
t
CMS
t
t
CMS
RRD
t
CMH
t
CMH
t
RAS
t
t
AS
AH
Row
Column
t
AS
Row
Row
t
DS
Data output
92CZ26A-653
t
t
RP
WR
t
AH
t
DH
TMP92CZ26A