Toshiba H1 Series Data Book page 148

3.7.12 Port J (PJ0 to PJ7)
PJ0 to PJ4 and PJ7 are 6-bit output port. Resetting sets the output latch PJ to "1", and
they output "1". PJ5 to PJ6 are 2-bit input/output port. In addition to functioning as port,
Port J also functions as output pins for SDRAM (
SDLUDQM, and SDCKE), SRAM (
and NDCLE). Above setting is used the function register PJFC.
But Output signal either SDRAM or SRAM for PJ0 to PJ2 are selected automatically
according to the setting of memory controller.
Reset
(on bit basis)
(on bit basis)
SRWR
Function
control2
PJFC2 write
Function
control
PJFC write
Selector
Selector
PJ write
SRLLB , SRLUB , SRWR
PJ read
SDRAS , SDCAS , SDWE , SDLLDQM, SDLUDQM, SDCKE
Figure 3.7.31 Port J0 to J4 and J7
92CZ26A-145
SDRAS
, and
SRLLB SRLUB
PJ0(
S
PJ1 (
PJ2(
PJ3(SDLLDQM)
PJ4(SDLUDQM)
PJ7(SDCKE)
TMP92CZ26A
, , , SDLLDQM,
SDCAS SDWE
) and NAND-Flash(NDALE
, )
SDRAS SRLLB
, )
SDCAS SRLUB
, )
SDWE SRWR