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3.8.4 ROM Page mode Access Control
This section describes ROM page mode accessing and how to set registers. ROM page mode
is set by PMEMCR.
(1)
Operation and how to set the registers
TMP92CZ26A supports ROM access with the page mode. The ROM access with the page
mode is specified only in CS2.
Setting PMEMCR<OPGE> to "1" sets the memory access of CS2 to ROM page mode access.
The number of read cycles is set by the PMEMCR<OPWR1:0>.
PMEMCR<OPWR1:0>
<OPWR1> <OPWR0>
0
0
1
1
Note: Set the number of waits "n" to the control register (BnCSL) in each block address area.
The page size (the number of bytes) of ROM in the CPU size is set to PMEMCR<PR1:0>.
When data is read out until a border of the set page, the controller completes the page reading
operation. The start data of the next page is read in the normal cycle. The following data is set
to page read again.
SDCLK
A2~A23
A0~A1
CS
2
RD
D0~D15
1 state (n-1-1-1 mode) (n ≥ 2)
0
2 state (n-2-2-2 mode) (n ≥ 3)
1
3 state (n-3-3-3 mode) (n ≥ 4)
0
4 state (n-4-4-4 mode) (n ≥ 5)
1
PMEMCR<PR1:0>
<PR1>
<PR0>
0
0
0
1
1
0
1
1
t
CYC
+ 0
t
AD3
t
RD3
Input
Data
Figure 3.8.5 Page mode access Timing
92CZ26A-199
Number of Cycle in a Page
ROM Page Size
64 bytes
32 bytes
16 bytes (Default)
8 bytes
+ 1
+ 2
t
t
AD2
AD2
t
t
HA
HA
Input
Data
TMP92CZ26A
+ 3
t
HA
t
AD2
t
HR
t
HA
Input
Input
Data
Data
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