Toshiba H1 Series Data Book page 493

(3-1) SPIST (SPI Status Register)
SPIST shows 4 statuses.
7
SPIST
bit Symbol
(824H)
Read/Write
After reset
Function
15
bit Symbol
(825H)
Read/Write
After reset
Function
(a) <TEMP>
For UNIT transmission, it is cleared to "0" when valid data exists in transmit register
(SPITD). It is set to "1" when no valid data exists.
For Sequential transmission, it is set to "1" when no valid data exists in transmit buffer.
(b) <TEND>
This bit is cleared to "0" when valid data to transmit exists in the shift register/FIFO buffer
or when transmission. It is set to "1" when no valid data exists in the transmit data
register/FIFO buffer and finish transmitting all the data.
(c) <REND>
For UNIT receiving, it is set to "1" when finish receiving and valid data was loaded to
receive data register (when valid data exists). It is cleared to "0" when no valid data exists
in receive register (SPIRD). It is set to "1" when no valid data exists or during receiving.
For Sequential receiving, it is set to "1" when valid data of 32 bytes exist in receive FIFO
after finish receiving last data. It is cleared to "0" even if having space of 1byte.
RFUL flag does not exist because meaning is the same with REND flag.
SPIST Register
6 5 4
14 13 12
Figure 3.17.9 SPIST Register
92CZ26A-490
3 2
TEMP TEND
R
1
Transmit FIFO Transmit
Status Status
0: during
0: no space transmission
1: having
or having
space
transmission
data
1: finish
11 10
TMP92CZ26A
1 0
REND
R
1 0
Receive
Status
0: during
receiving
or not having
receiving
data
1: finish or not
having space
9 8