Toshiba H1 Series Data Book page 364

Example: In case receive data N times
INTSBI interrupt (After transmitting data)
7 6 5 4 3 2 1 0
← X X X X X X X X
SBICR1
← SBIDBR
Reg.
End of interrupt
INTSBI interrupt (Receive data of 1st to (N−2) th)
7 6 5 4 3 2 1 0
← SBIDBR
Reg.
End of interrupt
INTSBI interrupt ((N−1) th Receive data)
7 6 5 4 3 2 1 0
← X X X 0 0 X X X
SBICR1
← SBIDBR
Reg.
End of interrupt
INTSBI interrupt (Nth Receive data)
7 6 5 4 3 2 1 0
← 0 0 1 0 0 X X X
SBICR1
← SBIDBR
Reg.
End of interrupt
INTSBI interrupt (After receiving data)
The process of generating stop condition
End of interrupt
Note: X: Don't care
Set the bit number of receive data and ACK.
Load the dummy data.
Load the data of 1st to (N−2)th.
Not generate acknowledge signal
Load the data of (N−1)th
Generate the clock for 1bit transmit
Receive the data of Nth.
Finish the transmit of data
92CZ26A-361
TMP92CZ26A