Toshiba H1 Series Data Book page 205

3.8.6 Cautions
(1) Note the timing between
If the load capacitance of the
select signal), it is possible that an unintended read cycle occurs due to a delay in the read
signal. Such an unintended read cycle may cause a trouble as in the case of (a) in Figure
3.8.6.
SDCLK
(60 MHz)
A23 to A0
CSm
CSn
RD
Example: When using an externally connected NOR flash which users JEDEC standard
commands, note that the toggle bit may not be read out correctly. If the read signal in the
cycle immediately preceding the access to the NOR flash does not go high in time, as
shown in Figure 3.8.7, an unintended read cycle like the one shown in (b) may occur.
NOR flash
chip select
When the toggle bit reverse with this unexpected read cycle, CPU always reads same
value of the toggle bit, and cannot read the toggle bit correctly.
To avoid this phenomenon, the data polling function control is recommended. Or use the
adjust timing function for rising edge of
generating this phenomenon.
and
CS RD
RD
Figure 3.8.6 Read Signal Delay Read Cycle
Memory access
SDCLK
(60 MHz)
A23 to A0
RD
Toggle bit
Figure 3.8.7 NOR Flash Toggle Bit Read Cycle
92CZ26A-202
(Read signal) is greater than that of the
(a)
Toggle bit RD cycle
(b)
(RDTMGCRn<BnTCRH1:0>) in order to avoid
RD
TMP92CZ26A
(Chip
CS