Toshiba H1 Series Data Book page 544

32bit micro controller tlcs-900/h1 series
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6. LD Bus
The data to be transferred to the LCD driver is output via a dedicated bus (LD23 to
LD0). The output format can be selected according to the input method of the LCD
driver to be used.
The LCDC reads data of the size corresponding to the specified LCD size from the
display RAM and transfers it to the external LCD driver via the data bus pin dedicated
to the LCD. Thus, the LCDC automatically issues a bus request to the CPU (to stop
CPU operation) when it needs to read data from the display RAM. The bus occupancy
rate of the LCDC varies depending on the display mode and the speed at which data is
read from the display RAM.
Display RAM
External SRAM
Internal RAM
External SDRAM
Note: When SDRAM is used, additional 9 clocks are needed as overhead time for reading each common (line)
data. When internal RAM is used, additional 1 clock is needed as overhead time for reading each common
(line) data. Additional 1 clock of overhead time is also needed when a change of blocks occur in the
internal RAM even if the common (line) remains the same.
The time the CPU stops operating while data for one common (line) is being
transferred is defined as t
t
STOP
SegNum : Number of display segments
K
Note: When SDRAM is used, overhead time is added as follows:
t
STOP
The bus occupancy rate indicates the proportion of the one common (line) update time t
is calculated by the following equation:
CPU bus occupancy rate = t
Valid Data Read Time
Bus Width
(f
SYS
16-bit
(2 + number of waits) / 2
32-bit
16-bit
which is represented by the following equation:
STOP,
= (SegNum × K / 8) × t
: Number of bits needed for displaying one pixel
Monochrome display
4-grayscale display
16-grayscale display
256-color display
4096-color display
65536-color display
262144-/16777216-color display
[S] = ( SegNum × K / 8 ) × t
LRD
[s] / LHSYNC [s: period]
STOP
92CZ26A-541
clocks/bytes)
**1/4
*1/2
LRD
K=1
K=2
K=4
K=8
K=12
K=16
K=24
) × 8 )
+ ((1 / f
SYS
TMP92CZ26A
Valid Data Read Time
t
(ns/bytes)
LRD
at f
= 60 MHz
SYS
16.6
**4.16
*8.33
occupied by t
and
LP
STOP

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