Toshiba H1 Series Data Book page 389

3.16.3.8 Setup Received Register
SetupReceived
bit Symbol
(07C8H)
Read/Write
After reset
Note : When EP0_FIFO is accessed register after wrote to this register, the recovery time of 2clock at 12MHz is
needed.
3.16.3.9 Current_Config Register
Current_Config
bit Symbol
(07C9H)
Read/Write
After reset
CONFIG[1:0] (Bit1 to bit0)
00: UNCONFIGURED
01: CONFIGURED1
10: CONFIGURED2
INTERFACE[1:0] (Bit3 to bit2)
00: INTERFACE0
01: INTERFACE1
10: INTERFACE2
ALTERNATE[1:0] (Bit5 to bit4)
00: ALTERNATE0
01: ALTERNATE1
10: ALTERNATE2
REMOTE WAKEUP (Bit7)
0: Disable
1: Enable
Note1: Config, INTERFACE and ALTERNATE each support 3 kinds (0,1 and 2).
Note2: If each request is controlled by S/W, this register is not set.
This register informs for the UDC that an application program recognized
INT_SETUP interrupt.
7 6
D7 D6
W W
0 0
If this register is accessed by an application program, the UDC release to disabling
access to EP0's FIFO RAM because the UDC recognized the device request is received.
This is to protect data stored in EP0 in the time from continuous request has been
asserted to an application program recognized INT_SETUP interrupt.
Therefore, write "00H" to this register when the device request in INT_SETUP
routine is recognized.
This register shows the present value that is set by SET_CONFIGURATION and
SET_INTERFACE.
7 6
REMOTEWAKEUP
R
0
Set to UNCONFIGURED by the host.
Set to CONFIGURED 1 by the host.
Set to CONFIGURED 2 by the host.
Set to INTERFACE 0 by the host.
Set to INTERFACE 1 by the host.
Set to INTERFACE 2 by the host.
Set to ALTERNATE 0 by the host.
Set to ALTERNATE 1 by the host.
Set to ALTERNATE 2 by the host.
Disabled remote wakeup by the host.
Enabled remote wakeup by the host.
5 4
D5 D4
W W
0 0
5 4
ALTERNATE[1] ALTERNATE[0] INTERFACE[1]
R R
0 0
92CZ26A-386
TMP92CZ26A
3 2
D3 D2 D1
W W W
0 0
3 2
INTERFACE[0] CONFIG[1]
R R
0 0
1 0
D0
W
0 0
1 0
CONFIG[0]
R R
0 0