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bit Symbol
USBINTFR2
(07F1H)
Read/Write
After reset
Prohibit
to read
Function
modify
write
Note: Above interrupt can release Halt state from IDLE2 mode. (IDLE1 and STOP mode can not be released.)
bit Symbol
USBINTFR3
(07F2H)
Read/Write
After reset
Prohibit
to read
Function
modify
write
Note: Above interrupt can release Halt state from IDLE2 mode. (IDLE1 and STOP mode can not be released.)
7
6
EP1_FULL_A
EP1_Empty_A
EP1_FULL_B
R/W
R/W
0
0
When read 0: Not generate interrupt
7
6
EP3_FULL_A
EP3_Empty_A
EP3_FULL_B
R/W
R/W
0
0
When read
0: Not generate interrupt
1: Generate interrupt
When write
0: Clear flag
1: −
•
EPx_FULL_A/B:
(When transmitting)
This is set to "1" when CPU full write data to FIFO_A/B.
(When receiving)
This is set to "1" when UDC full receive data to FIFO_A/B.
•
EPx_Empty_A/B:
(When transmitting)
This is set to "1" when FIFO become empty after transmission.
(When receiving)
This is set to "1" when FIFO become empty after CPU read all data from FIFO.
Note: The flag of EPx_FULL_A/B and EPx_Empty_A/B are not status flag. Therefore, check DATASET
register if the FIFO-status is needed.
5
4
3
EP1_Empty_B
EP2_FULL_A
R/W
R/W
R/W
0
0
When write 0: Clear flag
1: Generate interrupt
5
4
3
EP3_Empty_B
R/W
R/W
0
0
92CZ26A-373
2
1
EP2_Empty_A
EP2_FULL_B
R/W
R/W
0
0
0
1: −
2
1
TMP92CZ26A
0
EP2_Empty_B
R/W
0
0
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