Toshiba H1 Series Data Book page 555

3.19.4 Interrupt Function
The LCDC has two types of interrupts.
One is generated synchronous with the LLOAD signal and the other is generated
synchronous with the LLOAD signal that is output immediately after the LVSYNC
signal.
LCDMODE1<INTMODE> is used to switch between these two types of interrupts.
LVSYNC
LHSYNC
LLOAD
D15-0(VRAM Read)
Interrupt request
LCDMODE1<INTMODE>=0
Interrupt request
LCDMODE1<INTMODE>=1
When LCDMODE1<INTMODE>=0, an interrupt request is generated at the start of
each VRAM read before the LLOAD generates (once in each LLOAD period).
When LCDMODE1<INTMODE>=1, an interrupt request is generated at the start of
VRAM read before the first LLOAD generates (once in each LVSYNC period).
**The interrupt request generates when reading the data from VRAM at once. Since
reading from VRAM is executed by DMA with bus request to the CPU, DMA operation
is given priority. Thus CPU accepts interrupt immediately after reading the data from
VRAM.
bit Symbol
LCDMODE1
Read/Write
(0281H)
After reset
Function
Note: The LCDMODE1<INTMODE> setting must not be changed while the LCDC is operating. Be sure to set
LCDCTL0<START> to "0" to stop the LCDC operation before changing the interrupt setting.
7 6 5
LDC2 LDC1 LDC0
R/W R/W R/W
0 0 0
Data rotation function
(Supported for 64K-color: 16 bps
only)
000: Normal 100: 90-degree
001: Horizontal flip 101: Reserved
010: Vertical flip 110: Reserved
011: Vertical & 111: Reserved
horizontal flip
LCDMODE1 Register
4 3
LDINV AUTOINV
R/W R/W
0 0
LD bus Auto bus
inversion inversion
0: Normal 0: Disable
1: Invert 1: Enable
(Valid only
for TFT)
92CZ26A-552
TMP92CZ26A
2 1
INTMODE FREDGE SCPW2
R/W W
0 0
Interrupt LFR edge LD bus
selection Trance
0: LHSYNC Speed
0:LLOAD Front Edge
1:LVSYNC 1:LHSYNC 0: normal
Rear Edge 1: 1/3
0
W
0