Toshiba H1 Series Data Book page 247

3.11.3.2 Error Correction Methods
Hamming ECC
•
The ECC generator generates 44 bits of ECC for a page containing 512 bytes of valid data. The error
correction process must be performed in units of 256 bytes (22 bits of ECC). The following explains how
to implement error correction on 256 bytes of valid data using 22 bits of ECC.
•
If the NAND Flash to be used has a large-capacity page size (e.g. 2048 bytes), the error correction
process must be repeated several times to cover the entire page.
1) The calculated ECC and the ECC in the redundant area are rearranged, respectively,
so that the lower 2 bytes represent line parity (LPR15:0) and the upper 1 byte (of which
the upper 6 bits are valid) represents column parity (CPR7:2).
2) The two rearranged ECCs are XORed.
3) If the XOR result is 0 indicating an ECC match, the error correction process ends
normally (no error). If the XOR result is other than 0, it is checked whether or not the
error data can be corrected.
4) If the XOR result contains only one ON bit, it is determined that a single-bit error
exists in the ECC data itself and the error correction process terminates here (error not
correctable).
5) If each pair of bits 0 to 21 of the XOR result is either 01B or 10B, it is determined that
the error data is correctable and error correction is performed accordingly. If the XOR
result contains either 00B or 11B, it is determined that the error data is not correctable
and the error correction process terminates here.
Hexadecimal
Binary
6) The line and bit positions of the error are detected using the line parity and column
parity of the XOR result, respectively. The error bit thus detected is then inverted. This
completes the error correction process.
Example: When the XOR result is 26a65aH
Convert two bytes of line parity into one byte (10 → 1, 01 → 0).
Convert six bits of column parity into three bits (10 → 1 、 01 → 0).
Line parity:
Column parity:
Based on the above, error correction is performed by inverting the data in bit 5 at address 212.
An Example of Correctable
XOR Result
26a65a
10 01 10 00 Column parity
10 10 01 10 Line parity
01 01 10 10
10 10 01 10 01 01 10 10
1 1 0 1 0 0 1 1 = 212
10 01 10
1 0 1 = 5
92CZ26A-244
TMP92CZ26A
An Example of Uncorrectable
XOR Result
2ea65a
10 11 10 00 Column parity
10 10 01 10 Line parity
01 01 10 10
*Error at address 212
*Error in bit 5