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As shown in the diagram below, delay time of 0 to 127 pulses of the LCP0 clock can be
inserted in the LHSYNC signal.
Delay time = <HSD6:0>
Signal Name
LCP0 signal
LVSYNC signal
Reference LHSYNC
(with 0 delay)
LHSYNC signal
Delay control 1
bit Symbol
LCDHSDLY
Read/Write
(028FH)
After reset
Function
The phase of the LHSYNC signal can be inverted by the setting of LCDCTL1
<LVSP>.
(Enable width control)
LHSP=0
LHSP=1
LCDCTL1
bit Symbol
(0286H)
Read/Write
After reset
LCP0
phase
Function
0: Rising
1: Falling
LCDHSDLY Register
7
6
5
HSD6
HSD5
0
0
LHSYNC period
(Phase control)
LCD Control 1 Register
7
6
5
LCP0P
LHSP
LVSP
R/W
R/W
R/W
1
0
1
LHSYNC
LVSYNC
phase
phase
0: Rising
0: Rising
1: Falling
1: Falling
92CZ26A-530
4
3
HSD4
HSD3
HSD2
W
0
0
LHSYNC delay (bits 6-0)
LHSYNC signal
4
3
LLDP
R/W
0
LLOAD
phase
0: Rising
1: Falling
TMP92CZ26A
2
1
0
HSD1
HSD0
0
0
0
2
1
0
LVSW1
LVSW0
R/W
R/W
0
0
LVSYNC
enable time control
00 : 1 clock of LHSYNC
01 : 2 clocks of LHSYNC
10 : 3 clocks of LHSYNC
11 : Reserved
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