Toshiba H1 Series Data Book page 653

Page ROM Read Cycle
4.3.2
(1) 3-2-2-2 mode
Parameter
1 System clock period ( = T)
→ D0 ~ D15 input
2 A0, A1
→ D0 ~ D15 input
3 A2 ~ A23
→ D0 ~ D15 input
falling
4
RD
5 A0 ~ A23 Invalid → D0 ~ D15 hold
→ D0 ~ D15 hold
rising
6
RD
AC measuring condition
Note: The (a), (b) and (c) of "Symbol" in above table depend on the falling timing of
pin is set by MEMCR0<RDTMG1:0> in memory controller. If MEMCR0<RDTMG1:0> is set to "00", it
RD
correspond with (a) in above table, and "01" is (b), "10" is (c).
SDCLK
t
CYC
A2~A23
A0~A1
CS 2
t
RD
D0~D15
Symbol
t
CYC
t
AD2
t
AD3
t
RD3
t
HA
t
HR
+ 0
t
AD3 AD2
t t
RD3 HA
Data
input
92CZ26A-650
Variable
80 MHz 60 MHz
Min Max
12.5 266.6 12.5
2.0T − 18
3.0T − 18
19.5
2.5T − 18
0
0
+ 1 + 2
t
AD2
t
HA
Data Data
input input
TMP92CZ26A
Unit
16.6
7 15.2
31.8
ns
13 24
0 0
0 0
pin. The falling timing of
RD
+ 3
t
HA
t
AD2
t
HR
t
HA
Data
input