Toshiba H1 Series Data Book page 94

(2) HDMADn (DMA Transfer Destination Address Setting Register)
The HDMADn register is used to set the DMA transfer destination address. When the
destination address is updated by DMA execution, HDMADn is also updated.
HDMAD0 to HDMAD5 have the same configuration.
Although the bus sizing function is supported, the address alignment function is not
supported. Therefore, specify an even-numbered address for transferring 2 bytes and an
address that is an integral multiple of 4 for transferring 4 bytes.
bit Symbol
HDMADn
Read/Write
After reset
Function
bit Symbol DnDA15
Read/Write
After reset
Function
bit Symbol DnDA23
Read/Write
After reset
Function
Channel 0
Channel 1
Channel 2
Channel 3
Channel 4
Channel 5
Note: Read-modify-write instructions can be used on all these registers.
HDMADn Register
7 6 5
DnDA7 DnDA6 DnDA5
0 0 0
15 14 13
DnDA14 DnDA13
0 0 0
23 22 21
DnDA22 DnDA21
0 0 0
Destination address [23:16] for DMAn
Destination Destination
address address
[23: 16] [15: 8]
(0906H) (0905H)
(0916H) (0915H)
(0926H) (0925H)
(0936H) (0935H)
(0946H) (0945H)
(0956H) (0955H)
Figure 3.6.3 HDMADn Register
4 3
DnDA4 DnDA3
R/W
0 0
Destination address [7:0] for DMAn
12 11
DnDA12 DnDA11
R/W
0 0
Destination address [15:8] for DMAn
20 19
DnDA20 DnDA19
R/W
0 0
Destination
address
[7: 0]
HDMAD0
(0904H)
HDMAD1
(0914H)
HDMAD2
(0924H)
HDMAD3
(0934H)
HDMAD4
(0944H)
HDMAD5
(0954H)
92CZ26A-91
TMP92CZ26A
2 1 0
DnDA2 DnDA1 DnDA0
0 0 0
10 9 8
DnDA10 DnDA9 DnDA8
0 0 0
18 17 16
DnDA18 DnDA17 DnDA16
0 0 0