Toshiba H1 Series Data Book page 631

3.26 Multiply and Accumulate Calculation Unit (MAC)
The TMP92CZ26A includes a multiply-accumulate unit (MAC) capable of 32-bit × 32-bit + 64-bit
arithmetic operations at high speed. The MAC has the following features:
・One-cycle execution for all MAC operations (excluding register access time)
・Three operation modes : 1) 64-bit + 32-bit × 32-bit
・Support for signed/unsigned operations
・Support for integer operations only
3.26.1 Registers
The MAC in the TMP92CZ26A has one control register and three data registers. These
registers are connected to the CPU via a 32-bit bus and can be accessed in one system clock
(f ).
SYS
3.26.1.1 Control Register
The control register is used to control the operation of the MAC.
bit Symbol
Read/Write
MACCR
(1BFCH)
After reset
Prohibit
Overflow
Read-modify
flag
-write
0: No
Function
overflow
1: Overflow
occurred
Note 1: <MOPST> is write-only and it is read as
Note 2: Writing "1xx" to <MSTTG2:0> and writing "1" to <MOPST> can be executed in the same write cycle.
Note 3: <MOVF> is fixed two system clocks (f
2) 64-bit − 32-bit × 32-bit
3) 32-bit × 32-bit − 64-bit
MAC Control Register
7 6 5
MOVF MOPST MSTTG2
R/W W
0 0 0
Calculation Calculation start trigger
soft start
000: Write to MACMA<7:0>
0:Don't care 001: Write to MACMB<7:0>
1:Start 010: Write to MACMOR<7:0>
calculation 011: Write to MACMOR<39:32>
1xx: Write of "1" to <MOPST>
SYS
92CZ26A-628
4 3
MSTTG1 MSTTG0
R/W
0 0
"0".
) after calculation is started.
TMP92CZ26A
2 1
MSGMD MOPMD1 MOPMD0
R/W R/W
0 0
Sign mode Calculation mode
00: 64 + 32×32
0: Unsigned
01: 64 − 32×32
1: Signed
10: 32×32 − 64
11: Reserved
0
0