Toshiba H1 Series Data Book page 535

The number of pulses in the front dummy LHSYNC (vertical front porch) is specified
by LCDPRVSP<PLV6:0>. This delay time can be set in a range of 0 to 127 pulses of
the LCP0 clock.
Front dummy LHSYNC = <PLV6:0>
LCDPRVSP
bit Symbol
(028EH)
Read/Write
After reset
Function
The back dummy LHSYNC (vertical back porch) is defined as follows:
(<LVP9:0> + 1) − (valid LHSYNC: common size) − (front dummy LHSYNC:
<PLV6:0>)
Signal Name
LCP0
LLOAD signal
Note: The vertical back porch must be set to "1" or longer in all the cases (STN/TFT).
The enable width of the LLOAD signal is determined depending on the
LCDCTL0<LCP0OC> setting, as shown below.
LCDCTL0<LCP0OC> = 0 : Output at setting value in (LCDDLW) <LDW9:0>
LCDCTL0<LCP0OC> = 1 : Output at valid data
bit Symbol
LCDCTL0
(0285H) Read/Write
After reset
Function
Note: When select STN mode, LCP0 is output at valid data only regardless of the setting of <LCP0OC> bit.
LCD LVSYNC Pre Pulse Register
7 6 5
PLV6 PLV5
0 0
High width setting
LCP0 clock = 1, 2, 3 ... 1023 pulses (<PDT>=0) / 1024 pulses (<PDT>=1)
7 6
PIPE ALL0 FRMON
R/W R/W
0 0
PIP function Segment Frame divide
data setting
0: Disable
1: Enable 0: Normal 0: Disable
1: Always 1: Enable
output "0"
4 3
PLV4 PLV3
W
0 0
Front dummy LVSYNC (bits 6-0)
LCD Control 0 Register
5 4 3
–
R/W R/W
0 0
Always
write "0"
92CZ26A-532
TMP92CZ26A
2 1 0
PLV2 PLV1 PLV0
0 0 0
2 1
DLS LCP0OC START
R/W R/W
0 0
FR signal LCP0 (Note) LCDC
LCP0/Line 0: Always operation
selection output
1: At valid 0: Stop
0: Line data only 1: Start
1: LCP0 LLOAD
width
0: At setting
in register
1: At valid
data only
0
R/W
0