Table of Contents
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13.2.1 A/D Data Registers A to D (ADDRA to ADDRD).............................................. 415
13.2.2 A/D Control/Status Register (ADCSR)................................................................ 416
13.2.3 A/D Control Register (ADCR)............................................................................. 419
13.3 CPU Interface .................................................................................................................... 420
13.4 Operation ........................................................................................................................... 421
13.4.1 Single Mode (SCAN = 0) ..................................................................................... 421
13.4.2 Scan Mode (SCAN = 1) ....................................................................................... 423
13.4.3 Input Sampling and A/D Conversion Time.......................................................... 425
13.4.4 External Trigger Input Timing ............................................................................. 426
13.5 Interrupts............................................................................................................................ 427
13.6 Usage Notes ....................................................................................................................... 427
14.1 Overview............................................................................................................................ 433
14.1.1 Block Diagram...................................................................................................... 434
14.1.2 Register Configuration ......................................................................................... 434
14.2 System Control Register (SYSCR).................................................................................... 435
14.3 Operation ........................................................................................................................... 436
15.1 Overview............................................................................................................................ 437
15.2 Overview of Flash Memory............................................................................................... 438
15.2.1 Features ................................................................................................................ 438
15.2.2 Block Diagram...................................................................................................... 439
15.2.3 Pin Configuration ................................................................................................. 440
15.2.4 Register Configuration ......................................................................................... 440
15.3 Register Descriptions......................................................................................................... 441
15.3.1 Flash Memory Control Register (FLMCR).......................................................... 441
15.3.2 Erase Block Register (EBR)................................................................................. 445
15.3.3 RAM Control Register (RAMCR) ....................................................................... 446
15.3.4 Flash Memory Status Register (FLMSR)............................................................. 448
15.4 On-Board Programming Modes ........................................................................................ 449
15.4.1 Boot Mode............................................................................................................ 452
15.4.2 User Program Mode ............................................................................................. 457
15.5 Programming/Erasing Flash Memory................................................................................ 459
15.5.1 Program Mode...................................................................................................... 460
15.5.2 Program-Verify Mode .......................................................................................... 461
15.5.3 Erase Mode........................................................................................................... 463
15.5.4 Erase-Verify Mode ............................................................................................... 463
15.6 Flash Memory Protection .................................................................................................. 465
15.6.1 Hardware Protection............................................................................................. 465
15.6.2 Software Protection .............................................................................................. 467
15.6.3 Error Protection .................................................................................................... 467
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.................................................................................................................. 433
.................................................................................................................. 437
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