Module Standby Control Register (Mstcr) - Hitachi F-ZTAT H8/3039 Series Hardware Manual

17.2.2 Module Standby Control Register (MSTCR)

MSTCR is an 8-bit readable/writable register that controls output of the system clock (ø). It also
controls the module standby function, which places individual on-chip supporting modules in the
standby state. Module standby can be designated for the ITU, SCI0, SCI1, and A/D converter
modules.
Bit
PSTOP
Initial value
Read/Write
ø clock stop
Enables or disables
output of the system clock
MSTCR is initialized to H'40 by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bit 7—ø Clock Stop (PSTOP): Enables or disables output of the system clock (ø).
Bit 1
PSTOP Description
0 System clock output is enabled
1 System clock output is disabled
Bit 6—Reserved: This bit cannot be modified and is always read as 1.
Bit 5—Module Standby 5 (MSTOP5): Selects whether to place the ITU in standby.
Bit 5
MSTOP5 Description
0 ITU operates normally
1 ITU is in standby state
7 6
— MSTOP5
0 1
R/W —
Reserved bit
5 4
MSTOP4 MSTOP3
0 0
R/W R/W
Module standby 5 to 3, and 0
These bits select modules
to be placed in standby
3 2
—
0 0
R/W —
Reserved bit
(Initial value)
1 0
— MSTOP0
0 0
— R/W
(Initial value)
505