Hitachi F-ZTAT H8/3039 Series Hardware Manual page 572

Table A-1 Instruction Set (cont)
Mnemonic
INC.L #1, ERd
INC.L #2, ERd
DAA Rd
SUB.B Rs, Rd
SUB.W #xx:16, Rd
SUB.W Rs, Rd
SUB.L #xx:32, ERd
SUB.L ERs, ERd
SUBX.B #xx:8, Rd
SUBX.B Rs, Rd
SUBS.L #1, ERd
SUBS.L #2, ERd
SUBS.L #4, ERd
DEC.B Rd
DEC.W #1, Rd
DEC.W #2, Rd
DEC.L #1, ERd
DEC.L #2, ERd
DAS.Rd
MULXU. B Rs, Rd
MULXU. W Rs, ERd
MULXS. B Rs, Rd
MULXS. W Rs, ERd
DIVXU. B Rs, Rd
566
Operation
ERd32+1 → ERd32
L
ERd32+2 → ERd32
L
B Rd8 decimal adjust
→ Rd8
Rd8–Rs8 → Rd8
B
W Rd16–#xx:16 → Rd16
W Rd16–Rs16 → Rd16
L ERd32–#xx:32
→ ERd32
L ERd32–ERs32
→ ERd32
Rd8–#xx:8–C → Rd8
B
Rd8–Rs8–C → Rd8
B
ERd32–1 → ERd32
L
ERd32–2 → ERd32
L
ERd32–4 → ERd32
L
Rd8–1 → Rd8
B
W Rd16–1 → Rd16
W Rd16–2 → Rd16
ERd32–1 → ERd32
L
ERd32–2 → ERd32
L
B Rd8 decimal adjust
→ Rd8
Rd8 × Rs8 → Rd16
B
(unsigned multiplication)
W Rd16 × Rs16 → ERd32
(unsigned multiplication)
Rd8 × Rs8 → Rd16
B
(signed multiplication)
W Rd16 × Rs16 → ERd32
(signed multiplication)
Rd16 ÷ Rs8 → Rd16
B
(RdH: remainder,
RdL: quotient)
(unsigned division)
Addressing Mode and
Instruction Length (bytes)
2
2
2
2
4
2
6
2
2
2
2
2
2
2
2
2
2
2
2
2
2
4
4
2
No. of
States
Condition Code
I H N Z V C
— — —
— — —
— * * —
—
— (1)
— (1)
— (2)
— (2)
— (3)
— (3)
— — — — — —
— — — — — —
— — — — — —
— — —
— — —
— — —
— — —
— — —
— * * —
— — — — — —
— — — — — —
— — — —
— — — —
— — (6) (7) — —
*1
2
2
2
2
4
2
6
2
2
2
2
2
2
2
2
2
2
2
2
14
22
16
24
14