Pin States At Reset - Hitachi F-ZTAT H8/3039 Series Hardware Manual

D.2 Pin States at Reset
Reset in T1 State: Figure D-1 is a timing diagram for the case in which RES goes low during the
T1 state of an external memory access cycle. As soon as RES goes low, all ports are initialized to
the input state. AS, RD, and WR go high, and the data bus goes to the high-impedance state. The
address bus is initialized to the low output level 0.5 state after the low level of RES is sampled.
Sampling of RES takes place at the fall of the system clock (ø).
ø
RES
Internal
reset signal
Address bus
(modes 1, 3, 5)
AS (modes 1, 3, 5)
RD (read access)
(modes 1, 3, 5)
WR (write access)
(modes 1, 3, 5)
Data bus
(write access)
(modes 1, 3, 5)
I/O port
(modes 1, 3, 5 to 7)
Figure D-1 Reset during Memory Access (Reset during T1 State)
676
Access to external address
High
High
High
T T
1 2
T
3
H'000000
High impedance
High impedance