Table of Contents
Advertisement
Table D-1 Port States (cont)
Pin Name
Mode
P7
to P7
1, 3, 5 to 7
7
0
P8
1, 3, 5
0
6, 7
P8
1, 3, 5
1
6, 7
P9
to P9
1, 3, 5 to 7
5
0
PA
to PA
1, 3, 5 to 7
3
0
PA
to PA
3
6
4
1, 5, 6, 7
PA
3
7
1, 5, 6, 7
PB
, PB
to
1, 3, 5 to 7
7
5
PB
0
Legend
H:
High
L:
Low
T:
High-impedance state
keep: Input pins are in the high-impedance state; output pins maintain their previous state.
DDR: Data direction register bit
ADRCR: Address control register
Notes: 1 Masked ROM version. Dedicated FWE input pin for the F-ZTAT version.
2 Low output only when WDT overflows causes a reset.
Hardware
Standby
Reset State
Mode
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
L
T
T
T
T
T
Software
Program
Standby
Execution State
Mode
Sleep Mode
T
Input port
keep
I/O port
keep
I/O port
T [DDR = 0]
Input port [DDR = 0]
H [DDR = 1]
H [DDR = 1]
keep
I/O port
keep
I/O port
keep
I/O port
[ADRCR = 0]
(ADRCR = 0)
T
A
to A
21
[ADRCR = 1]
(ADRCR = 1)
keep
I/O port
keep
I/O port
T
A
20
keep
I/O port
keep
I/O port
23
675
Advertisement
Table of Contents
