Register Configuration - Hitachi F-ZTAT H8/3039 Series Hardware Manual

8.1.4 Register Configuration

Table 8-3 summarizes the ITU registers.
Table 8-3 ITU Registers
Channel Address*
Common H'FF60
H'FF61
H'FF62
H'FF63
H'FF90
H'FF91
0 H'FF64
H'FF65
H'FF66
H'FF67
H'FF68
H'FF69
H'FF6A
H'FF6B
H'FF6C
H'FF6D
1 H'FF6E
H'FF6F
H'FF70
H'FF71
H'FF72
H'FF73
H'FF74
H'FF75
H'FF76
H'FF77
Notes: 1. The lower 16 bits of the address are indicated.
2. Only 0 can be written, to clear flags.
1
Name
Timer start register
Timer synchro register
Timer mode register
Timer function control register
Timer output master enable register
Timer output control register
Timer control register 0
Timer I/O control register 0
Timer interrupt enable register 0
Timer status register 0
Timer counter 0 (high)
Timer counter 0 (low)
General register A0 (high)
General register A0 (low)
General register B0 (high)
General register B0 (low)
Timer control register 1
Timer I/O control register 1
Timer interrupt enable register 1
Timer status register 1
Timer counter 1 (high)
Timer counter 1 (low)
General register A1 (high)
General register A1 (low)
General register B1 (high)
General register B1 (low)
Abbre-
viation R/W
TSTR R/W
TSNC R/W
TMDR R/W
TFCR R/W
TOER R/W
TOCR R/W
TCR0 R/W
TIOR0 R/W
TIER0 R/W
2
TSR0 R/(W)*
TCNT0H R/W
TCNT0L R/W
GRA0H R/W
GRA0L R/W
GRB0H R/W
GRB0L R/W
TCR1 R/W
TIOR1 R/W
TIER1 R/W
2
TSR1 R/(W)*
TCNT1H R/W
TCNT1L R/W
GRA1H R/W
GRA1L R/W
GRB1H R/W
GRB1L R/W
Initial
Value
H'E0
H'E0
H'80
H'C0
H'FF
H'FF
H'80
H'88
H'F8
H'F8
H'00
H'00
H'FF
H'FF
H'FF
H'FF
H'80
H'88
H'F8
H'F8
H'00
H'00
H'FF
H'FF
H'FF
H'FF
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