Hitachi F-ZTAT H8/3039 Series Hardware Manual page 317

Single-chip microcomputer
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Example of Non-Overlapping TPC Output (Example of Four-Phase Complementary Non-
Overlapping Output): Figure 9-7 shows an example of the use of TPC output for four-phase
complementary non-overlapping pulse output.
TCNT value
GRB
TCNT
GRA
H'0000
NDRA
95
PADR
00
TP
7
TP
6
TP
5
TP
4
TP
3
TP
2
TP
1
TP
0
The ITU channel to be used as the output trigger channel is set up so that GRA and GRB are output
compare registers and the counter will be cleared by compare match B. The TPC output trigger
period is set in GRB. The non-overlap margin is set in GRA. The IMIEA bit is set to 1 in TIER to enable
IMFA interrupts.
H'FF is written in PADDR and NDERA, and bits G3CMS1, G3CMS0, G2CMS1, and G2CMS0 are set in
TPCR to select compare match in the ITU channel set up in step 1 as the output trigger.
Bits G3NOV and G2NOV are set to 1 in TPMR to select non-overlapping output. Output data H'95 is
written in NDRA.
The timer counter in this ITU channel is started. When compare match B occurs, outputs change from
1 to 0. When compare match A occurs, outputs change from 0 to 1 (the change from 0 to 1 is delayed
by the value of GRA). The IMFA interrupt service routine writes the next output data (H'65) in NDRA.
Four-phase complementary non-overlapping pulse output can be obtained by writing H'59, H'56, H'95...
at successive IMFA interrupts.
Figure 9-7 Non-Overlapping TPC Output Example (Four-Phase Complementary
65
59
95
05
65
41
Non-overlap margin
Non-Overlapping Pulse Output)
56
95
59
50
56
14
65
95
05
65
Time
307

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