Hitachi F-ZTAT H8/3039 Series Hardware Manual page 402

Bits 3 to 0—Operate in the same way as for the normal SCI. For details, see section 11.2.7, Serial
Status Register (SSR).
However, the setting conditions for the TEND bit are as shown below.
Bit 2
TEND Description
0 Transmission is in progress
[Clearing conditions]
•
When 0 is written to TDRE after reading TDRE = 1
1 End of transmission
[Setting conditions]
•
Upon reset and in standby mode
•
When the TE bit in SCR is 0 and the ERS bit is also 0
•
When TDRE = 1 and ERS = 0 (normal transmission) 2.5 etu after transmission of
a 1-byte serial character
Note: etu: Elementary Time Unit (time for transfer of 1 bit)
(Initial value)
393