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5.4.3 Interrupt Response Time
Table 5-5 indicates the interrupt response time from the occurrence of an interrupt request until the
first instruction of the interrupt service routine is executed.
Table 5-5 Interrupt Response Time
No.
Item
1
Interrupt priority decision
2
Maximum number of states
until end of current instruction
3
Saving PC and CCR to stack
4
Vector fetch
5
Instruction prefetch*
6
Internal processing*
Total
Notes: 1. 1 state for internal interrupts.
2. Prefetch after the interrupt is accepted and prefetch of the first instruction in the interrupt
service routine.
3. Internal processing after the interrupt is accepted and internal processing after prefetch.
4. The number of states increases if wait states are inserted in external memory access.
104
2
3
On-Chip
Memory
2 States
1
1
2*
2*
1 to 23
1 to 27
4
8
4
8
4
8
4
4
19 to 41
31 to 57
External Memory
8-Bit Bus
3 States
1
2*
4
1 to 31*
4
12*
4
12*
4
12*
4
43 to 73
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