Hitachi F-ZTAT H8/3039 Series Hardware Manual page 456

Bit 3—RAM Select (RAMS): Is used with bits 2 to 1 to reassign an area to RAM (see table 15-5).
The initial setting for this bit is 0 in Modes 5, 6, and 7 (internal flash memory enabled) and
programming is enabled.* In modes other than 5 to 7, 0 is always read and writing is disabled.
It is initialized by a reset and in hardware standby mode. It is not initialized in software standby
mode.
When bit 3 is set, all flash-memory blocks are protected from programming and erasing.
Bits 2 to 1—RAM2 to RAM1: These bits are used with bit 3 to reassign an area to RAM (see
table 15-5). The initial setting for this bit is 0 in Modes 5, 6, and 7 (internal flash memory enabled)
and programming is enabled.* In modes other than 5 to 7, 0 is always read and writing is disabled.
They are initialized by a reset and in hardware standby mode. They are not initialized in software
standby mode.
Bit 0—Reserved: This bit cannot be modified and is always read as 1.
Note: * Flash memory emulation by RAM is not supported for Mode 6 (single chip normal
mode), so programming is possible, but do not set 1.
When performing flash memory emulation by RAM, the RAME bit in SYSCR must be
set to 1.
Table 15-5 RAM Area Reassignment
RAM Area
H'FFF800 to H'FFFBFF
H'000000 to H'0003FF
H'000400 to H'0007FF
H'000800 to H'000BFF
H'000C00 to H'000FFF
ROM block
EB0–EB3
(H'00000–H'00FFF)
Figure 15-2 Example of Overlap ROM Area and RAM Area
Bit 3
RAMS
0
1
1
1
1
ROM area
H'00000
EB0
H'003FF
H'00400
EB1
H'007FF
H'00800
Mapping RAM
EB2
H'00BFF
H'00C00
EB3
H'00FFF
Bit 2 Bit 1
RAM2 RAM1
0/1 0/1
0 0
0 1
1 0
1 1
RAM area
ROM
selection
Real RAM
area
RAM
selection
area
RAM
Emulation State
No emulation
Mapping RAM
H'FEF10
H'FF7FF
RAM overlap area
H'FF800
(H'FF800–H'FFBFF)
H'FFBFF
H'FFC00
H'FFF0F
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