Erase Block Register (Ebr) - Hitachi F-ZTAT H8/3039 Series Hardware Manual

15.3.2

Erase Block Register (EBR)

EBR is an 8-bit register that designates the flash memory block for erasure. EBR is initialized to
H'00 by a reset, in hardware standby mode, or software standby mode, when a high level is not
input to the FWE terminal, or when the FLMCR SWE bit is 0 when a high level is applied to the
FWE terminal. When a bit is set in EBR, the corresponding block can be erased. Other blocks are
erase - protected. The blocks are erased block by block. Therefore, set only one bit in EBR; do not
set bits in EBR to erase two or more blocks at the same time.
Each bit in EBR cannot be set until the SWE bit in FLMCR is set. The flash memory block
configuration is shown in table 15-4. To erase all the blocks, erase each block sequentially.
This LSI does not support the on-board programming mode in mode 6, so bits in this register
cannot be set to 1 in mode 6.
Bit
Modes 1 Initial value
to 4, and 6
R/W
Modes 5 Initial value
and 7 R/W
Bits 7 to 0—Block 7 to 0 (EB7 to EB0): These bits select blocks (EB7 to EB0) to be erased.
Bits 7 to 0:
EB7 to EB0 Description
0 Block EB7 to EB0 is not selected.
1 Block EB7 to EB0 is selected.
Note: Set each bit of EBR to H'00 except when erasing.
7 6
EB5
EB7 EB6
0 0
R R
0 0
R/W R/W R/W
5 4 3
EB4
EB3
0 0 0
R R R
0 0 0
R/W R/W
2 1
EB2 EB1 EB0
0 0
R R R
0 0
R/W R/W R/W
(Initial value)
0
0
0
445