Bus Control Signal Timing - Hitachi F-ZTAT H8/3039 Series Hardware Manual

6.3.2 Bus Control Signal Timing

8-Bit, Three-State-Access Areas: Figure 6-3 shows the timing of bus control signals for an 8-bit,
three-state-access area. Wait states can be inserted.
ø
Address bus
AS
RD
Read
access
D to D
7 0
WR
Write
access
D to D
7 0
Figure 6-3 Bus Control Signal Timing for 8-Bit, Three-State-Access Area
Bus cycle
T
1
External address
T
2
Valid
Valid
T
3
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