Hitachi F-ZTAT H8/3039 Series Hardware Manual page 285

Contention between General Register Read and Input Capture: If an input capture signal
occurs during the T
3
See figure 8-66.
ø
Address
Internal read signal
Input capture signal
GR
Internal data bus
Figure 8-66 Contention between General Register Read and Input Capture
state of a general register read cycle, the value before input capture is read.
General register read cycle
T T
1 2
GR address
X
X
T
3
M
275