Hitachi F-ZTAT H8/3039 Series Hardware Manual page 683

Reset in T2 State: Figure D-2 is a timing diagram for the case in which RES goes low during the
T2 state of an external memory access cycle. As soon as RES goes low, all ports are initialized to
the input state. AS, RD, and WR go high, and the data bus goes to the high-impedance state. The
address bus is initialized to the low output level 0.5 state after the low level of RES is sampled.
The same timing applies when a reset occurs during a wait state (T
ø
RES
Internal
reset signal
Address bus
(modes 1, 3, 5)
AS (modes 1, 3, 5)
RD (read access)
(modes 1, 3, 5)
WR (write access)
(modes 1, 3, 5)
Data bus
(write access)
(modes 1, 3, 5)
I/O port
(modes 1, 3, 5 to 7)
Figure D-2 Reset during Memory Access (Reset during T2 State)
Access to external address
T T
1 2
).
W
T
3
H'000000
High impedance
High impedance
677