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Table 15-8 Hardware Protection
Item
Description
FWE pin protection •
•
Reset/standby
protection
•
•
Error protection
Notes: 1. Two modes: program-verify and erase-verify.
2. The RAM area that overlapped flash memory is deleted.
3. All blocks become unerasable and specification by block is impossible.
4. For more information, see section 15.9, Notes on Flash Memory Programming/Erasing.
5. See sections 4.2.2, Reset Sequence and 15.9, Notes on Flash Memory
Programming/Erasing. This LSI requires a minimum reset time during operation of 20
system clocks.
466
When a low level is input to the FWE pin,
FLMCR and EBR are initialized, and the
program/erase-protected state is
4
entered.*
In a reset (including a WDT overflow
reset) and in standby mode, FLMCR and
EBR are initialized, and the
program/erase-protected state is entered.
In a reset via the RES pin, the reset state
is not entered unless the RES pin is held
low until oscillation stabilizes after
powering on (The minimum oscillation
stabilization time is 20ms). In the case of
a reset during operation, hold the RES
pin low for at least 20 system clock
5
cycles. *
When a microcomputer operation error
(error generation (FLER=1)) was
detected while flash memory was being
programmed/erased, error protection is
enabled. At this time, the FLMCR and
EBR settings are held, but
programming/erasing is aborted at the
time the error was generated. Error
protection is released only by a reset via
the RES pin or a WDT reset, or in the
hardware standby mode.
Function
Program
Erase
2
3
No*
No*
3
No
No*
3
No
No*
1
Verify*
No
No
Yes
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