Pin Configuration; Register Configuration - Hitachi F-ZTAT H8/3039 Series Hardware Manual

15.2.3

Pin Configuration

The flash memory is controlled by means of the pins shown in table 15-2.
Table 15-2 Flash Memory Pins
Pin Name
Reset
Flash write enable
Mode 2
Mode 1
Mode 0
Transmit data
Receive data
Notes: The transmit data and receive data pins are used in boot mode.
* In the mask ROM versions, the FWE pin functions as the RESO pin.
15.2.4

Register Configuration

The registers used to control the on-chip flash memory when enabled are shown in table 15-3.
Table 15-3 Flash Memory Registers
Register Name
Flash memory control register
Erase block register
RAM control register
Flash memory status register
Notes: 1. Lower 16 bits of the address.
2. When a high level is input to the FWE pin, the initial value is H'80.
The registers in table 15-3 are used in the flash memory versions only. Reading the corresponding
addresses in a mask ROM version will always return 1s, and writes to these addresses are disabled.
440
Abbreviation I/O
RES
Input
FWE* Input
MD Input
2
MD Input
1
MD Input
0
TxD Output
1
RxD Input
1
Abbreviation
FLMCR
EBR
RAMCR
FLMSR
Function
Reset
Flash program/erase protection by hardware
Sets this LSI operating mode
Sets this LSI operating mode
Sets this LSI operating mode
Serial transmit data output
Serial receive data input
R/W Initial Value
R/W H'00*
R/W H'00
R/W H'F1
R H'7F
Address*
2
H'FF40
H'FF42
H'FF47
H'FF4D
1