Hitachi F-ZTAT H8/3039 Series Hardware Manual page 104

5.2.4 IRQ Enable Register (IER)
IER is an 8-bit readable/writable register that enables or disables IRQ
interrupt requests.
Bit 7
—
Initial value
0
Read/Write —
Reserved bits
IER is initialized to H'00 by a reset and in hardware standby mode.
Bits 7, 6, 3, and 2—Reserved: These bits cannot be modified and are always read as 0.
Bits 5, 4, 1, and 0—IRQ
These bits enable or disable IRQ5E, IRQ4E, IRQ1E, IRQ0Ε interrupts.
Bits 5, 4, 1, and 0
IRQ5E, IRQ4E,
IRQ1E, and IRQ0E
0
1
92
6 5
— IRQ5E IRQ4E
0 0
— R/W
IRQ to IRQ enable
5
These bits enable or disable
IRQ and IRQ
5
, IRQ , IRQ , and IRQ
5 4 1
Description
IRQ , IRQ , IRQ , IRQ
5 4 1
IRQ , IRQ , IRQ , IRQ
5 4 1
4 3
—
0 0
R/W R/W R/W
Reserved bits
4
interrupts
4
Enable (IRQ5E, IRQ4E, IRQ1E, IRQ0E):
0
interrupts are disabled
0
interrupts are enabled
0
, IRQ , IRQ , and IRQ
0 1 4
2 1 0
— IRQ1E IRQ0E
0 0 0
R/W R/W
IRQ to IRQ enable
1 0
These bits enable or disable
IRQ and IRQ
1
5
interrupts
0
(Initial value)