Block Diagram; Register Configuration - Hitachi F-ZTAT H8/3039 Series Hardware Manual

14.1.1 Block Diagram

Figure 14-1 shows a block diagram of the on-chip RAM.
Legend
SYSCR: System control register
Note: * Lower 20 bits of the address
Figure 14-1 RAM Block Diagram (H8/3039 in Modes 1, 5 and 7)

14.1.2 Register Configuration

The on-chip RAM is controlled by the system control register (SYSCR). Table 14-2 gives the
address and initial value of SYSCR.
Table 14-2 RAM Control Register
Address* Name
H'FFF2 System control register
Note: * Lower 16 bits of the address
434
Internal data bus (upper 8 bits)
Internal data bus (lower 8 bits)
Bus interface
*
H'FEF10
H'FEF12*
On-chip RAM
H'FFF0E *
Even addresses
Abbreviation
SYSCR
*
H'FEF11
*
H'FEF13
H'FFF0F *
Odd addresses
R/W
R/W
SYSCR
Initial Value
H'0B