Register Settings - Hitachi F-ZTAT H8/3039 Series Hardware Manual

12.3.4

Register Settings

Table 12-3 shows a bit map of the registers used by the smart card interface.
Bits indicated as 0 or 1 must be set to the value shown. The setting of other bits is described
below.
Table 12-3 Smart Card Interface Register Settings
Register Bit 7
SMR 0
BRR BRR7
SCR TIE
TDR TDR7
SSR TDRE
RDR RDR7
SCMR —
Note: — : Unused bit.
SMR Setting: The O/E bit is cleared to 0 if the IC card is of the direct convention type, and set to
1 if of the inverse convention type.
Bits CKS1 and CKS0 select the clock source of the on-chip baud rate generator. See section
12.3.5, Clock.
BRR Setting: BRR is used to set the bit rate. See section 12.3.5, Clock, for the method of
calculating the value to be set.
SCR Setting: The function of the TIE, RIE, TE, and RE bits is the same as for the normal SCI.
For details, see section 11, Serial Communication Interface.
Bit CKE0 specifies the clock output. Set these bits to 0 if a clock is not to be output, or to 1 if a
clock is to be output.
398
Bit 6 Bit 5
0 1
BRR6 BRR5
RIE TE
TDR6 TDR5
RDRF ORER
RDR6 RDR5
— —
Bit
Bit 4 Bit 3
O/E 1
BRR4 BRR3
RE 0
TDR4 TDR3
ERS PER
RDR4 RDR3
— SDIR
Bit 2 Bit 1
0 CKS1
BRR2 BRR1
0 0
TDR2 TDR1
TEND 0
RDR2 RDR1
SINV —
Bit 0
CKS0
BRR0
CKE0
TDR0
0
RDR0
SMIF