Hitachi F-ZTAT H8/3039 Series Hardware Manual page 8

9.2.2 Port A Data Register (PADR) .............................................................................. 289
9.2.3 Port B Data Direction Register (PBDDR)............................................................ 290
9.2.4 Port B Data Register (PBDR)............................................................................... 290
9.2.5 Next Data Register A (NDRA) ............................................................................ 291
9.2.6 Next Data Register B (NDRB) ............................................................................. 293
9.2.7 Next Data Enable Register A (NDERA).............................................................. 295
9.2.8 Next Data Enable Register B (NDERB) .............................................................. 296
9.2.9 TPC Output Control Register (TPCR) ................................................................. 297
9.2.10 TPC Output Mode Register (TPMR) ................................................................... 300
9.3 Operation ........................................................................................................................... 302
9.3.1 Overview .............................................................................................................. 302
9.3.2 Output Timing ...................................................................................................... 303
9.3.3 Normal TPC Output ............................................................................................. 304
9.3.4 Non-Overlapping TPC Output ............................................................................. 306
9.3.5 TPC Output Triggering by Input Capture ............................................................ 308
9.4 Usage Notes ....................................................................................................................... 309
9.4.1 Operation of TPC Output Pins ............................................................................. 309
9.4.2 Note on Non-Overlapping Output........................................................................ 309
Section 10 Watchdog Timer
10.1 Overview............................................................................................................................ 311
10.1.1 Features................................................................................................................... 311
10.1.2 Block Diagram...................................................................................................... 312
10.1.3 Pin Configuration ................................................................................................. 312
10.1.4 Register Configuration ......................................................................................... 313
10.2 Register Descriptions......................................................................................................... 314
10.2.1 Timer Counter (TCNT) ........................................................................................ 314
10.2.2 Timer Control/Status Register (TCSR) ................................................................ 315
10.2.3 Reset Control/Status Register (RSTCSR) ............................................................ 317
10.2.4 Notes on Register Access ..................................................................................... 319
10.3 Operation ........................................................................................................................... 321
10.3.1 Watchdog Timer Operation.................................................................................. 321
10.3.2 Interval Timer Operation...................................................................................... 322
10.3.3 Timing of Setting of Overflow Flag (OVF) ......................................................... 323
10.3.4 Timing of Setting of Watchdog Timer Reset Bit (WRST) .................................. 324
10.4 Interrupts............................................................................................................................ 325
10.5 Usage Notes ....................................................................................................................... 325
Section 11 Serial Communication Interface
11.1 Overview............................................................................................................................ 327
11.1.1 Features ................................................................................................................ 327
11.1.2 Block Diagram...................................................................................................... 329
11.1.3 Input/Output Pins.................................................................................................. 330
vi
............................................................................................ 311
............................................................... 327