Hitachi F-ZTAT H8/3039 Series Hardware Manual page 406

Single-chip microcomputer
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The operation sequence is as follows.
[1] When the data line is not in use it is in the high-impedance state, and is fixed high with a pull-
up resistor.
[2] The transmitting station starts a date transfer of one frame. The data frame starts with a start bit
(Ds, low-level). Then 8 data bits (D0 to D7) and a parity bit (Dp) follows.
[3] With the Smart Card interface, the data line then returns to the high-impedance state. The data
line is pulled high with a pull-up resistor.
[4] The receiving station carries out a parity check.
If there is no parity error and the data is received normally, the receiving station waits for
reception of the next data.
If a parity error occurs, however, the receiving station outputs an error signal (DE, low-level)
to request retransmission of the data. After outputting the error signal for the prescribed length
of time, the receiving station places the signal line in the high-impedance state again. The
signal line is pulled high again by a pull-up resistor.
[5] If the transmitting station does not receive an error signal, it proceeds to transmit the next data
frame.
If it does receive an error signal, however, it returns to step [2] and retransmits the erroneous
data.
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F-ztat h8/3039F-ztat h8/3038F-ztat h8/3037F-ztat h8/3036

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