Hsr Host Transmit Data Empty (Htde) Bit 1 - Motorola DSP56367 User Manual

HDI08 generates a receive data full DMA request, if enabled by a DSP core DMA Channel. If
HRDF is set when HRIE is set, a host receive data interrupt request is generated. HRDF can
also be cleared by the host processor using the initialize function.
8.5.4.2

HSR Host Transmit Data Empty (HTDE) Bit 1

The HTDE bit indicates that the host transmit data register (HOTX) is empty and can be
written by the DSP core. HTDE is set when the HOTX register is transferred to the
RXH:RXM:RXL registers. HTDE is cleared when HOTX is written by the DSP core. If
HTDE is set the HDI08 generates a transmit data empty DMA request, if enabled by a DSP
core DMA Channel. If HTDE is set when HTIE is set, a host transmit data interrupt request is
generated. HTDE can also be set by the host processor using the initialize function.
8.5.4.3 HSR Host Command Pending (HCP) Bit 2
The HCP bit indicates that the host has set the HC bit and that a host command interrupt is
pending. The HCP bit reflects the status of the HC bit in the command vector register (CVR).
HC and HCP are cleared by the HDI08 hardware when the interrupt request is serviced by the
DSP core. The host can clear HC, which also clears HCP.
8.5.4.4 HSR Host Flags 0,1 (HF0,HF1) Bits 3-4
HF0 and HF1 bits are used as a general-purpose flags for host to DSP communication. HF0
and HF1 may be set or cleared by the host. HF0 and HF1 reflect the status of host flags HF0
and HF1 in the ICR register on the host side.
These two flags are not designated for any specific purpose but are general-purpose flags.
They can be used individually or as encoded pairs in a simple host to DSP communication
protocol, implemented in both the DSP and the host Processor software.
8.5.4.5 HSR Reserved Bits 5-6, 8-15
These bits are reserved. They read as zero and should be written with zero for future
compatibility.
8.5.4.6 HSR DMA Status (DMA) Bit 7
The DMA status bit is set when the DMA mode of operation is enabled, and is cleared when
the DMA mode is disabled. The DMA mode is enabled under the following conditions:
• HCR bits HDM[2:0] = 100 and the host processor has enabled the DMA mode by
setting either or both the ICR bits HM1 and HM0
• Either or both of the HCR bits HDM1 and HDM0 have been set
When the DMA bit is zero, the channel not in use can be used for polled or interrupt operation
by the DSP.
MOTOROLA
HDI08 – DSP-Side Programmer's Model
DSP56367
Host Interface (HDI08)
8-11