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In the synchronous mode when RFSD is set, the FSR pin becomes the OF1 output flag or the
Transmitter Buffer Enable, according to the TEBE control bit. If RFSD is cleared, then the
FSR pin becomes the IF1 input flag. See Table 10-1 and Table 10-8.
10.3.3.10
RCCR Receiver High Frequency Clock Direction (RHCKD) - Bit 23
The Receiver High Frequency Clock Direction (RHCKD) bit selects the source of the receiver
high frequency clock when in the asynchronous mode (SYN=0), and the IF2/OF2 flag
direction in the synchronous mode (SYN=1).
In the asynchronous mode when RHCKD is set, the internal clock generator becomes the
source of the receiver high frequency clock, and is the output on the HCKR pin. In the
asynchronous mode when RHCKD is cleared, the receiver high frequency clock source is
external; the internal clock generator is disconnected from the HCKR pin, and an external
clock source may drive this pin.
When RHCKD is cleared, HCKR is an input; when RHCKD is set, HCKR is an output.
In the synchronous mode when RHCKD is set, the HCKR pin becomes the OF2 output flag. If
RHCKD is cleared, then the HCKR pin becomes the IF2 input flag. See Table 10-1 and
Table 10-9.
MOTOROLA
Table 10-8 FSR Pin Definition Table
Control Bits
SYN
TEBE
0
X
0
X
1
0
1
0
1
1
1
1
Table 10-9 HCKR Pin Definition Table
Control Bits
SYN
RHCKD
0
0
1
1
DSP56367
Enhanced Serial Audio Interface (ESAI)
ESAI Programming Model
FSR Pin
RFSD
0
FSR input
1
FSR output
0
IF1
1
OF1
0
reserved
1
Transmitter
Buffer
Enable
HCKR PIN
0
HCKR input
1
HCKR output
0
IF2
1
OF2
10-29
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